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| author | Egor Yusov <egor.yusov@gmail.com> | 2018-05-31 15:35:34 +0000 |
|---|---|---|
| committer | Egor Yusov <egor.yusov@gmail.com> | 2018-05-31 15:35:34 +0000 |
| commit | c6bfb3bdcb4215eba7061090c25fa7604a1a0d44 (patch) | |
| tree | 9b980c7331aecc3cbd110b51b2cd46f59ed6c8cf /Tests/TestApp/assets/TestComputeShaders.lua | |
| parent | Moved Stride to vertex layout desc; updated tests (diff) | |
| download | DiligentEngine-c6bfb3bdcb4215eba7061090c25fa7604a1a0d44.tar.gz DiligentEngine-c6bfb3bdcb4215eba7061090c25fa7604a1a0d44.zip | |
Updated back buffer format to match the one from the swap chain in the tests
Diffstat (limited to 'Tests/TestApp/assets/TestComputeShaders.lua')
| -rw-r--r-- | Tests/TestApp/assets/TestComputeShaders.lua | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Tests/TestApp/assets/TestComputeShaders.lua b/Tests/TestApp/assets/TestComputeShaders.lua index 85cc46b..ba9fb38 100644 --- a/Tests/TestApp/assets/TestComputeShaders.lua +++ b/Tests/TestApp/assets/TestComputeShaders.lua @@ -238,7 +238,7 @@ RenderPSO = PipelineState.Create { InputIndex = 0, BufferSlot = 0, NumComponents = 3, ValueType = "VT_FLOAT32", IsNormalized = false, Stride = 4*4}, { InputIndex = 1, BufferSlot = 1, NumComponents = 2, ValueType = "VT_FLOAT32", IsNormalized = false, Stride = 4*4} }, - RTVFormats = {"TEX_FORMAT_RGBA8_UNORM_SRGB"}, + RTVFormats = {extBackBufferFormat}, PrimitiveTopology = "PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP" } } |