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2 <head>
3 <title>SubV / RV32I reference</title>
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77 </style>
78 </head>
79 <body>
80 <h1>SubV / RV32I instruction set <b>reference</b></h1>
81 <h2>instructions</h2>
82 <table cellspacing="0">
83 <tr>
84 <th>
85 <i>37</i>/<b>lui</b>
86 </th>
87 <td>
88 <i>*</i>/<b class="reg dst">rd</b>
89 </td>
90 <td colspan="3"/>
91 <td>
92 <i>*</i>/<b class="imm src">imm20</b>
93 </td>
94 </tr>
95 <tr class="light">
96 <th>
97 <i>17</i>/<b>auipc</b>
98 </th>
99 <td>
100 <i>*</i>/<b class="reg dst">rd</b>
101 </td>
102 <td colspan="3"/>
103 <td>
104 <i>*</i>/<b class="imm src">off20</b>
105 </td>
106 </tr>
107 <tr>
108 <th>
109 <i>6f</i>/<b>jal</b>
110 </th>
111 <td>
112 <i>*</i>/<b class="reg dst">rd</b>
113 </td>
114 <td colspan="3"/>
115 <td>
116 <i>*</i>/<b class="imm jmp">off21</b>
117 </td>
118 </tr>
119 <tr class="light">
120 <th>
121 <i>67</i>/<b>jalr</b>
122 </th>
123 <td>
124 <i>*</i>/<b class="reg dst">rd</b>
125 </td>
126 <td>
127 <i>0</i>/<b>subop</b>
128 </td>
129 <td>
130 <i>*</i>/<b class="reg src">rs</b>
131 </td>
132 <td />
133 <td>
134 <i>*</i>/<b class="imm jmp">off12</b>
135 </td>
136 </tr>
137 <tr>
138 <th>
139 <i>63</i>/<b>branch</b>
140 </th>
141 <td />
142 <td>
143 <i>*</i>/<b class="branch-op">subop</b>
144 </td>
145 <td>
146 <i>*</i>/<b class="reg src">rs1</b>
147 </td>
148 <td>
149 <i>*</i>/<b class="reg src">rs2</b>
150 </td>
151 <td>
152 <i>*</i>/<b class="imm jmp">off13</b>
153 </td>
154 </tr>
155 <tr class="light">
156 <th>
157 <i>13</i>/<b>opi</b>
158 </th>
159 <td>
160 <i>*</i>/<b class="reg dst">rd</b>
161 </td>
162 <td>
163 <i>*</i>/<b class="op-op">subop</b>
164 </td>
165 <td>
166 <i>*</i>/<b class="reg src">rs</b>
167 </td>
168 <td />
169 <td>
170 <i>*</i>/<b class="imm src">imm12</b>
171 </td>
172 </tr>
173 <tr class="light">
174 <th>
175 <i>13</i>/<b>opi</b>
176 </th>
177 <td>
178 <i>*</i>/<b class="reg dst">rd</b>
179 </td>
180 <td>
181 <i>*</i>/<b class="op-op">subop</b>
182 <i>*</i>/<b class="op-mode">mode</b>
183 </td>
184 <td>
185 <i>*</i>/<b class="reg src">rs</b>
186 </td>
187 <td />
188 <td>
189 <i>*</i>/<b class="imm src">imm7</b>
190 </td>
191 </tr>
192 <tr>
193 <th>
194 <i>33</i>/<b>opr</b>
195 </th>
196 <td>
197 <i>*</i>/<b class="reg dst">rd</b>
198 </td>
199 <td>
200 <i>*</i>/<b class="op-op">subop</b>
201 <i>*</i>/<b class="op-mode">mode</b>
202 </td>
203 <td>
204 <i>*</i>/<b class="reg src">rs1</b>
205 </td>
206 <td>
207 <i>*</i>/<b class="reg src">rs2</b>
208 </td>
209 <td />
210 </tr>
211 <tr class="light">
212 <th>
213 <i>03</i>/<b>load</b>
214 </th>
215 <td>
216 <i>*</i>/<b class="reg dst">rd</b>
217 </td>
218 <td />
219 <td colspan="2">
220 <i>*</i>/<b class="width src">width</b>
221 <i>*</i>/<b class="reg src">rs</b>
222 <i>*</i>/<b class="imm src">off12</b>
223 </td>
224 <td />
225 </tr>
226 <tr>
227 <th>
228 <i>23</i>/<b>store</b>
229 </th>
230 <td colspan="2">
231 <i>*</i>/<b class="width dst">width</b>
232 <i>*</i>/<b class="reg dst">rd</b>
233 <i>*</i>/<b class="imm dst">off12</b>
234 </td>
235 <td>
236 <i>*</i>/<b class="reg src">rs</b>
237 </td>
238 <td colspan="2" />
239 </tr>
240 <tr class="light">
241 <th>
242 <i>73</i>/<b>system</b>
243 </th>
244 <td>
245 <i>*</i>/<b class="reg dst">rd</b>
246 </td>
247 <td>
248 <i>*</i>/<b class="sys-op">subop</b>
249 </td>
250 <td>
251 <i>*</i>/<b class="reg src">rs</b>
252 </td>
253 <td>
254 <i>*</i>/<b class="imm">csr</b>
255 </td>
256 <td />
257 </tr>
258 <tr class="light">
259 <th>
260 <i>73</i>/<b>system</b>
261 </th>
262 <td>
263 <i>*</i>/<b class="reg dst">rd</b>
264 </td>
265 <td>
266 <i>*</i>/<b class="sys-op">subop</b>
267 </td>
268 <td />
269 <td>
270 <i>*</i>/<b class="imm">csr</b>
271 </td>
272 <td>
273 <i>*</i>/<b class="imm src">imm5</b>
274 </td>
275 </tr>
276 <tr class="light">
277 <th>
278 <i>73</i>/<b>system</b>
279 </th>
280 <td />
281 <td>
282 <i>0</i>/<b class="sys-op">subop</b>/priv
283 </td>
284 <td />
285 <td colspan="2">
286 <i>0</i>/<b>funct12</b>/ecall
287 </td>
288 </tr>
289 <tr class="light">
290 <th>
291 <i>73</i>/<b>system</b>
292 </th>
293 <td />
294 <td>
295 <i>0</i>/<b class="sys-op">subop</b>/priv
296 </td>
297 <td />
298 <td colspan="2">
299 <i>1</i>/<b>funct12</b>/ebreak
300 </td>
301 </tr>
302 </table>
303 <h2>special parts</h2>
304 <table cellspacing="0">
305 <tr class="light">
306 <th colspan="2" rowspan="2">
307 <b>reg</b> (<b class="reg dst">rd</b>, <b class="reg src">rs*</b>)
308 </th>
309 <td>
310 00/<b>zero</b> 01/<b>ra</b> 02/<b>sp</b> 03/<b>gp</b> 04/<b>tp</b>
311 </td>
312 <td>
313 05/<b>t0</b>..07/<b>t2</b> 1c/<b>t3</b>..1f/<b>t6</b>
314 </td>
315 </tr>
316 <tr class="light">
317 <td>
318 8/<b>s0</b> 9/<b>s1</b> 12/<b>s2</b>..1b/<b>s7</b>
319 </td>
320 <td>
321 0a/<b>a0</b>..11/<b>a7</b>
322 </td>
323 </tr>
324 <tr>
325 <th colspan="2"><b>width</b></th>
326 <td>0/<b>b</b> 1/<b>h</b> 2/<b>w</b></td>
327 <td>4/<b class="src">bu</b> 5/<b class="src">hu</b></td>
328 </tr>
329 <tr class="light">
330 <th rowspan="4"><b>subop</b></th>
331 <th><b class="branch-op">branch</b></th>
332 <td>0/<b>==</b> 1/<b>!=</b> 4/<b>&lt;</b> 5/<b>>=</b></td>
333 <td>6/<b>&lt;u</b> 7/<b>>=u</b></td>
334 </tr>
335 <tr>
336 <th rowspan="2"><b class="op-op">opi</b>/<b class="op-op">opr</b></th>
337 <td colspan="2">
338 <i>00</i>/<b class="op-mode">mode</b>/norm:&emsp;
339 0/<b>add</b> 1/<b>sll</b> 2/<b>slt</b> 3/<b>sltu</b>
340 4/<b>xor</b> 5/<b>srl</b> 6/<b>or</b> 7/<b>and</b>
341 </td>
342 </tr>
343 <tr>
344 <td colspan="2">
345 <i>20</i>/<b class="op-mode">mode</b>/alt:&nbsp;&emsp;
346 0/<b>sub</b> 5/<b>sra</b>
347 </td>
348 </tr>
349 <tr class="light">
350 <th><b class="sys-op">system</b></th>
351 <td>1/<b>csrrw</b> 2/<b>csrrs</b> 3/<b>csrrc</b></td>
352 <td>5/<b>csrrwi</b> 6/<b>csrrsi</b> 7/<b>csrrci</b></td>
353 </tr>
354 <tr>
355 <th><b>csr</b></th>
356 <td />
357 <td colspan="2">
358 see <a href="https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMFDQC-and-Priv-v1.11/riscv-privileged-20190608.pdf#section2.2">priviledged spec, sect 2.2</a>
359 </td>
360 </tr>
361 </table>
362 </body>
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