git.s-ol.nu subv / 6783dba
update examples s-ol 21 days ago
8 changed file(s) with 83 addition(s) and 83 deletion(s). Raw diff Collapse all Expand all
1111
1212 == code 0x80400000
1313 # load mhartid CSR into t0, trap all but first Hart
14 # 73/system 5/rd/t0 2/funct3/csrrs 0/rs/x0 f14/imm12/mhartid
14 # 73/system 5/rd/t0 2/funct3/csrrs 0/rs/x0 f14/csr12/mhartid
1515 # 63/branch 1/subop/!= 5/rs/t0 0/rs/x0 0/off13
1616
1717 main:
1919
2020 # print HELLO_WHATSURNAME
2121 37/lui a/rd/a0 HELLO_WHATSURNAME/imm20hi
22 13/opi 0/subop/add a/rd/a0 a/rs/a0 HELLO_WHATSURNAME/imm12lo
22 13/opi a/rd/a0 0/subop/add a/rs/a0 HELLO_WHATSURNAME/imm12lo
2323 6f/jal 1/rd/ra print/off21
2424
2525 37/lui a/rd/a0 Name/imm20hi
26 13/opi 0/subop/add a/rd/a0 a/rs/a0 Name/imm12lo
26 13/opi a/rd/a0 0/subop/add a/rs/a0 Name/imm12lo
2727 6f/jal 1/rd/ra read/off21
2828
2929 # print HELLO_
3030 37/lui a/rd/a0 HELLO_/imm20hi
31 13/opi 0/subop/add a/rd/a0 a/rs/a0 HELLO_/imm12lo
31 13/opi a/rd/a0 0/subop/add a/rs/a0 HELLO_/imm12lo
3232 6f/jal 1/rd/ra print/off21
3333
3434 # print Name
3535 37/lui a/rd/a0 Name/imm20hi
36 13/opi 0/subop/add a/rd/a0 a/rs/a0 Name/imm12lo
36 13/opi a/rd/a0 0/subop/add a/rs/a0 Name/imm12lo
3737 6f/jal 1/rd/ra print/off21
3838
3939 # print NICETOMEETU
4040 37/lui a/rd/a0 NICETOMEETU/imm20hi
41 13/opi 0/subop/add a/rd/a0 a/rs/a0 NICETOMEETU/imm12lo
41 13/opi a/rd/a0 0/subop/add a/rs/a0 NICETOMEETU/imm12lo
4242 6f/jal 1/rd/ra print/off21
4343
4444 # infinite loop
4646
4747 init:
4848 # initialize UART0
49 # load 0x10010000 (UART0) into t0
50 37/lui 5/rd/t0 0x10000/imm20
49 # load 0x10000000 (UART0) into t0
50 37/lui 5/rd/t0 10000/imm20
5151
5252 # disable interrupts
53 23/store 0/width/byte 5/rs/t0 0/rs/x0 1/off12
53 23/store 0/width/b 5/rs/t0 1/off12 0/rs/x0
5454
5555 # enable DLAB
56 13/opi 0/subop/add 6/rd/t1 0/rs/x0 80/imm12
57 23/store 0/width/byte 5/rs/t0 6/rs/t1 3/off12
56 13/opi 6/rd/t1 0/subop/add 0/rs/x0 80/imm12
57 23/store 0/width/b 5/rs/t0 3/off12 6/rs/t1
5858
5959 # max speed = 38400bps
60 13/opi 0/subop/add 6/rd/t1 0/rs/x0 3/imm12
61 23/store 0/width/byte 5/rs/t0 6/rs/t1 0/off12
62 23/store 0/width/byte 5/rs/t0 0/rs/x0 1/off12
60 13/opi 6/rd/t1 0/subop/add 0/rs/x0 3/imm12
61 23/store 0/width/b 5/rs/t0 0/off12 6/rs/t1
62 23/store 0/width/b 5/rs/t0 1/off12 0/rs/x0
6363
6464 # disable DLAB
65 13/opi 0/subop/add 6/rd/t1 0/rs/x0 3/imm12
66 23/store 0/width/byte 5/rs/t0 6/rs/t1 3/off12
65 13/opi 6/rd/t1 0/subop/add 0/rs/x0 3/imm12
66 23/store 0/width/b 5/rs/t0 3/off12 6/rs/t1
6767
6868 # enable fifo, clear, watermark=14b
69 13/opi 0/subop/add 6/rd/t1 0/rs/x0 c7/imm12
70 23/store 0/width/byte 5/rs/t0 6/rs/t1 2/off12
69 13/opi 6/rd/t1 0/subop/add 0/rs/x0 c7/imm12
70 23/store 0/width/b 5/rs/t0 2/off12 6/rs/t1
7171
7272 # set dtr, srs, aux2
73 13/opi 0/subop/add 6/rd/t1 0/rs/x0 b/imm12
74 23/store 0/width/byte 5/rs/t0 6/rs/t1 4/off12
73 13/opi 6/rd/t1 0/subop/add 0/rs/x0 b/imm12
74 23/store 0/width/b 5/rs/t0 4/off12 6/rs/t1
7575
76 13/opi 0/subop/add 6/rd/t1 0/rs/x0 1/imm12
77 23/store 0/width/byte 5/rs/t0 6/rs/t1 1/off12
76 13/opi 6/rd/t1 0/subop/add 0/rs/x0 1/imm12
77 23/store 0/width/b 5/rs/t0 1/off12 6/rs/t1
7878
7979 # return
8080 67/jalr 0/subop 0/rd/x0 1/rs/ra 0/off12
8181
8282 old:
83 # load 3 into t1
84 13/opi 0/subop/add 6/rd/t1 0/rs/x0 3/imm12
8583 # set "data terminal ready" and "request to send" bits in MCR
86 23/store 0/width/byte 5/rs/t0 6/rs/t1 4/off12
84 13/opi 6/rd/t1 0/subop/add 0/rs/x0 3/imm12
85 23/store 0/width/b 5/rs/t0 4/off12 6/rs/t1
8786 # return
8887 67/jalr 0/subop 0/rd/x0 1/rs/ra 0/off12
8988
9089 print:
9190 # print a C-string from a0
92 # load 0x10010000 (UART0) into t0
93 37/lui 5/rd/t0 0x10000/imm20
91 # load 0x10000000 (UART0) into t0
92 37/lui 5/rd/t0 10000/imm20
9493 print:loop:
95 # load unsigned byte at a0
96 03/load 4/subop/byte 6/rd/t1 a/rs/a0 0/imm12
94 # load unsigned byte at [a0] into t1
95 03/load 6/rd/t1 4/width/bu a/rs/a0 0/off12
9796 # break loop if zero
9897 63/branch 0/subop/== 6/rs/t1 0/rs/x0 print:break/off13
9998 print:spin:
10099 # spin if FIFO is full (thr_empty = UART+5 & 0x20)
101 03/load 4/subop/byte 7/rd/t2 5/rs/t0 5/imm12
102 13/opi 7/subop/and 7/rd/t2 7/rs/t2 20/imm12
100 03/load 7/rd/t2 4/width/bu 5/rs/t0 5/off12
101 13/opi 7/rd/t2 7/subop/and 7/rs/t2 20/imm12
103102 63/branch 0/subop/== 7/rs/t2 0/rs/x0 print:spin/off13
104 # print char
105 23/store 0/width/byte 5/rs/t0 6/rs/t1 0/off12
103 # store char from t1 at [t0]
104 23/store 0/width/b 5/rs/t0 0/off12 6/rs/t1
106105 # increment a0
107 13/opi 0/subop/add a/rd/a0 a/rs/a0 1/imm12
106 13/opi a/rd/a0 0/subop/add a/rs/a0 1/imm12
108107 # jump back up
109108 6f/jal 0/rd/x0 print:loop/off21
110109 print:break:
111110 # return
112 67/jalr 0/subop 0/rd/x0 1/rs/ra 0/off12
111 67/jalr 0/rd/x0 0/subop 1/rs/ra 0/off12
113112
114113 read:
115114 # read a C-string into a0
116115 # load 0x10000000 (UART0) into t0
117116 37/lui 5/rd/t0 0x10000/imm20
118117 # load 0x0a (\n) into t1
119 13/opi 0/subop/add 6/rd/t1 0/rs/x0 0a/imm12
118 13/opi 6/rd/t1 0/subop/add 0/rs/x0 0a/imm12
120119
121120 read:loop:
122121 # spin if FIFO is empty (data_ready = UART+5 & 1)
123 03/load 4/subop/byte 7/rd/t2 5/rs/t0 5/imm12
124 13/opi 7/subop/and 7/rd/t2 7/rs/t2 1/imm12
122 03/load 7/rd/t2 4/width/bu 5/rs/t0 5/imm12
123 13/opi 7/rd/t2 7/subop/and 7/rs/t2 1/imm12
125124 63/branch 0/subop/== 7/rs/t2 0/rs/x0 read:loop/off13
126 # load unsigned byte into t2
127 03/load 4/subop/byte 7/rd/t2 5/rs/t0 0/imm12
125 # read char at [t0] into t2
126 03/load 7/rd/t2 4/width/bu 5/rs/t0 0/imm12
128127 # break loop if newline (t2 == t1)
129128 63/branch 0/subop/== 7/rs/t2 6/rs/t1 read:break/off13
130 # store char at a0
131 23/store 0/width/byte a/rs/a0 7/rs/t2 0/off12
129 # store char from t1 at [a0]
130 23/store 0/width/b a/rs/a0 7/rs/t2 0/off12
132131 # increment a0
133 13/opi 0/subop/add a/rd/a0 a/rs/a0 1/imm12
132 13/opi a/rd/a0 0/subop/add a/rs/a0 1/imm12
134133 # jump back up
135134 6f/jal 0/rd/x0 read:loop/off21
136135 read:break:
137136 # return
138 67/jalr 0/subop 0/rd/x0 1/rs/ra 0/off12
137 67/jalr 0/rd/x0 0/subop 1/rs/ra 0/off12
139138
140139
141140 == data 0x80500000
Binary diff not shown
0 == code 0x80000000
0 == code 0x80400000
11 # repeatedly print "Hi\n"
22 # main:
3 # load 0x10010000 (UART0) into t0
4 37/7 05/5 10010/20
3 # load 0x10000000 (UART0) into t0
4 37/7 05/5 10000/20
55 # store 0x48 (H) in UART0+0
66 13/7 06/5 0/3 00/5 048/12
7 23/7 00/5 2/3 05/5 06/5 00/7
7 23/7 00/5 0/3 05/5 06/5 00/7
88 # store 0x69 (i) in UART0+0
99 13/7 06/5 0/3 00/5 069/12
10 23/7 00/5 2/3 05/5 06/5 00/7
10 23/7 00/5 0/3 05/5 06/5 00/7
1111 # store 0x0a (\n) in UART0+0
1212 13/7 06/5 0/3 00/5 00a/12
13 23/7 00/5 2/3 05/5 06/5 00/7
13 23/7 00/5 0/3 05/5 06/5 00/7
1414 # jump back up to the top
1515 6f/7 00/5 ff/8 1/1 3f2/10 1/1
0 == code 0x80000000
0 == code 0x80400000
11 # repeatedly print "Hi\n"
22 # main:
3 # load 0x10010000 (UART0) into t0
4 b7 02 01 10
3 # load 0x10000000 (UART0) into t0
4 b7 02 00 10
55 # store 0x48 (H) in UART0+0
66 13 03 80 04
7 23 a0 62 00
7 23 80 62 00
88 # store 0x69 (i) in UART0+0
99 13 03 90 06
10 23 a0 62 00
10 23 80 62 00
1111 # store 0x0a (\n) in UART0+0
1212 13 03 a0 00
13 23 a0 62 00
13 23 80 62 00
1414 # jump back up to the top
1515 6f f0 5f fe
0 == code 0x80000000
0 == code 0x80400000
11 # repeatedly print "Hi\n"
22 main:
3 # load 0x10010000 (UART0) into t0
4 37/lui 5/rd/t0 0x10010/imm20
3 # load 0x10000000 (UART0) into t0
4 37/lui 5/rd/t0 10000/imm20
55 # store 0x48 (H) in UART0+0
66 13/opi 0/subop/add 6/rd/t1 0/rs/x0 48/imm12
7 23/store 2/width/word 5/rs/t0 6/rs/t1 0/off12
7 23/store 0/width/byte 5/rs/t0 0/off12 6/rs/t1
88 # store 0x69 (i) in UART0+0
99 13/opi 0/subop/add 6/rd/t1 0/rs/x0 69/imm12
10 23/store 2/width/word 5/rs/t0 6/rs/t1 0/off12
10 23/store 0/width/byte 5/rs/t0 0/off12 6/rs/t1
1111 # store 0x0a (\n) in UART0+0
1212 13/opi 0/subop/add 6/rd/t1 0/rs/x0 0a/imm12
13 23/store 2/width/word 5/rs/t0 6/rs/t1 0/off12
13 23/store 0/width/byte 5/rs/t0 0/off12 6/rs/t1
1414 # jump back up to the top
1515 6f/jal 0/rd/x0 main/off21
0 == code 0x80000000
0 == code 0x80400000
11 # repeatedly print "Hi\n"
22 # main:
3 # load 0x10010000 (UART0) into t0
4 37/u 5/rd 10010/imm20
3 # load 0x10000000 (UART0) into t0
4 37/u 5/rd 10000/imm20
55 # store 0x48 (H) in UART0+0
66 13/i 6/rd 0/funct3 0/rs 48/imm12
7 23/s 5/rs1 0/imm12 2/funct3 6/rs2
7 23/s 0/funct3 5/rs1 0/imm12 6/rs2
88 # store 0x69 (i) in UART0+0
99 13/i 6/rd 0/funct3 0/rs 69/imm12
10 23/s 5/rs1 0/imm12 2/funct3 6/rs2
10 23/s 0/funct3 5/rs1 0/imm12 6/rs2
1111 # store 0x0a (\n) in UART0+0
1212 13/i 6/rd 0/funct3 0/rs a/imm12
13 23/s 5/rs1 0/imm12 2/funct3 6/rs2
13 23/s 0/funct3 5/rs1 0/imm12 6/rs2
1414 # jump back up to the top
1515 6f/j 0/rd -1c/imm21
0 == code 0x80000000
0 == code 0x80400000
11 # repeatedly print "Hi\n"
22 main:
3 # load 0x10010000 (UART0) into t0
4 37/u 5/rd 10010/imm20
3 # load 0x10000000 (UART0) into t0
4 37/u 5/rd 10000/imm20
55 # store 0x48 (H) in UART0+0
66 13/i 6/rd 0/funct3 0/rs 48/imm12
7 23/s 5/rs1 0/imm12 2/funct3 6/rs2
7 23/s 0/funct3 5/rs1 0/imm12 6/rs2
88 # store 0x69 (i) in UART0+0
99 13/i 6/rd 0/funct3 0/rs 69/imm12
10 23/s 5/rs1 0/imm12 2/funct3 6/rs2
10 23/s 0/funct3 5/rs1 0/imm12 6/rs2
1111 # store 0x0a (\n) in UART0+0
1212 13/i 6/rd 0/funct3 0/rs a/imm12
13 23/s 5/rs1 0/imm12 2/funct3 6/rs2
13 23/s 0/funct3 5/rs1 0/imm12 6/rs2
1414 # jump back up to the top
1515 6f/j 0/rd main/off21
00 == code 0x80400000
1 # trap all but first Hart (a0 = mhartid)
2 # 63/branch 1/subop/!= a/rs/a0 0/rs/x0 0/off13
1 # load mhartid CSR into t0, trap all but first Hart
2 # 73/system 5/rd/t0 2/funct3/csrrs 0/rs/x0 f14/csr12/mhartid
3 # 63/branch 1/subop/!= 5/rs/t0 0/rs/x0 0/off13
34
45 main:
56 # a0 = &message
67 # . load high bits
78 37/lui a/rd/a0 Message/imm20hi
89 # . add low bits
9 13/opi 0/subop/add a/rd/a0 a/rs/a0 Message/imm12lo
10 13/opi a/rd/a0 0/subop/add a/rs/a0 Message/imm12lo
1011 # call print
1112 6f/jal 1/rd/ra print/off21
1213 loop:
1819 37/lui 5/rd/t0 0x10000/imm20
1920 print:loop:
2021 # load unsigned byte at a0
21 03/load 4/subop/byte 6/rd/t1 a/rs/a0 0/imm12
22 03/load 6/rd/t1 4/width/bu a/rs/a0 0/imm12
2223 # break loop if zero
2324 63/branch 0/subop/== 6/rs/t1 0/rs/x0 print:break/off13
2425 print:spin:
2526 # spin if FIFO is full (thr_emtpy = UART+5 & 0x20)
26 03/load 4/subop/byte 7/rd/t2 5/rs/t0 5/imm12
27 13/opi 7/subop/and 7/rd/t2 7/rs/t2 20/imm12
27 03/load 7/rd/t2 4/width/bu 5/rs/t0 5/imm12
28 13/opi 7/rd/t2 7/subop/and 7/rs/t2 20/imm12
2829 63/branch 0/subop/== 7/rs/t2 0/rs/x0 print:spin/off13
2930 # print char
30 23/store 2/width/word 5/rs/t0 6/rs/t1 0/off12
31 23/store 2/width/w 5/rs/t0 0/off12 6/rs/t1
3132 # increment a0
32 13/opi 0/subop/add a/rd/a0 a/rs/a0 1/imm12
33 13/opi a/rd/a0 0/subop/add a/rs/a0 1/imm12
3334 # jump back up
3435 6f/jal 0/rd/x0 print:loop/off21
3536 print:break:
3637 # return
37 67/jalr 0/subop 0/rd/x0 1/rs/ra 0/off12
38 67/jalr 0/rd/x0 0/subop 1/rs/ra 0/off12
3839
3940 == data 0x80500000
4041 Message: