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authors-ol <s+removethis@s-ol.nu>2022-11-25 20:46:09 +0000
committers-ol <s+removethis@s-ol.nu>2022-12-06 20:45:24 +0000
commit3cdadf788442e28a04d3d7a0eb8df9cb88d331aa (patch)
tree8cf44959d995cf49491f4294ff0d62ea95b55021 /case/case.py
parentfix clearances between tracks and holes (diff)
downloadhardware-3cdadf788442e28a04d3d7a0eb8df9cb88d331aa.tar.gz
hardware-3cdadf788442e28a04d3d7a0eb8df9cb88d331aa.zip
case: add "template" svg output
Diffstat (limited to 'case/case.py')
-rw-r--r--case/case.py71
1 files changed, 54 insertions, 17 deletions
diff --git a/case/case.py b/case/case.py
index 0886964..cb49f0a 100644
--- a/case/case.py
+++ b/case/case.py
@@ -160,7 +160,7 @@ def make_plate(
bottom = plate.faces('<Z').val().outerWire()
- if 'cover' in outputs:
+ if 'cover' in outputs or 'template' in outputs:
cover_pos = list(gridify(shape2points('''
O O O O O O O O O
@@ -257,14 +257,17 @@ def make_plate(
.moveTo(*gridpos((2, 5.185)))
.circle(5.850)
.cutThruAll()
+ )
+ cover_final = (cover
.rotate((0,0,0), (0,0,1), -90)
.translate((0, 0, top_space+top_thick))
)
- results.append(('cover', 'step', cover))
- results.append(('cover', 'dxf', cover.section(top_space+top_thick - 1.5)))
- results.append(('cover.cb', 'dxf', cover.section(top_space+top_thick - 3.5)))
+ if 'cover' in outputs:
+ results.append(('cover', 'step', cover_final))
+ results.append(('cover', 'dxf', cover_final.section(top_space+top_thick - 1.5)))
+ results.append(('cover.cb', 'dxf', cover_final.section(top_space+top_thick - 3.5)))
if 'fill.outer' in outputs:
wire = (
@@ -389,7 +392,7 @@ def make_plate(
results.append(('plate.top', 'step', plate))
results.append(('plate.top', 'dxf', plate.section(top_space+top_thick)))
- if 'plate.bottom' in outputs:
+ if 'plate.bottom' in outputs or 'template' in outputs:
plate = (
cq.Workplane("XY")
.newObject([bottom])
@@ -410,7 +413,9 @@ def make_plate(
.offset2D(expand, kind='intersection')
.extrude(bottom_thick)
+ )
+ plate_final = (plate
# USB plug cutout
.cut(
cq.Workplane("XY")
@@ -445,8 +450,8 @@ def make_plate(
)
if 'feet' in kwargs:
- plate = (
- plate
+ plate_final = (
+ plate_final
# silicon pads
.pushPoints(kwargs['feet'])
@@ -455,10 +460,10 @@ def make_plate(
)
if 'mounting_holes' in kwargs:
- plate = kwargs['mounting_holes'](plate)
+ plate_final = kwargs['mounting_holes'](plate_final)
# stamp cutout
- plate = plate.cut(
+ plate_final = plate_final.cut(
cq.Workplane("XY")
.moveTo(35.2 - 126, 185.4 - 26)
.rect(25 + 2, 25 + 2)
@@ -470,7 +475,7 @@ def make_plate(
)
# USB cutout
- plate = plate.cut(
+ plate_final = plate_final.cut(
cq.Workplane("XY")
.moveTo(25.603341 - 126, 245.209203 - 26)
.rect(10, 9.2 + 0.5)
@@ -481,14 +486,40 @@ def make_plate(
.rotate((25.603341 - 126, 245.209203 - 26, 0), (25.603341 - 126, 245.209203 - 26, 1), -30)
)
- plate = (
- plate
+ plate_final = (
+ plate_final
.rotate((0,0,0), (0,0,1), -90)
.translate((0, 0, -(pcb_thick + bottom_space + bottom_thick)))
)
- results.append(('plate.bottom', 'step', plate))
- results.append(('plate.bottom', 'dxf', plate.section(-(pcb_thick + bottom_space + bottom_thick/2))))
+ if 'plate.bottom' in outputs:
+ results.append(('plate.bottom', 'step', plate_final))
+ results.append(('plate.bottom', 'dxf', plate_final.section(-(pcb_thick + bottom_space + bottom_thick/2))))
+
+ if 'template' in outputs:
+ tpl = (cq.Workplane("XY")
+ .add(plate.edges('|Z').fillet(fillet).section())
+
+ .add(cover.section())
+
+ .add(
+ cq.Workplane("XY")
+ .pushPoints(key_pos)
+ .polygon(6, radius - 2)
+ .extrude(cover_h)
+ .edges('|Z')
+ .fillet(4)
+ .section(cover_h)
+ )
+ )
+
+ tpl_final = tpl.rotate((0,0,0), (0,0,1), -90)
+ results.append(('template', 'svg', tpl_final, {
+ "showAxes": False,
+ "projectionDir": (0, 0, 1),
+ "showHidden": False,
+ }))
+
return results
@@ -583,7 +614,8 @@ if __name__ == "__main__" or show_object:
if show_object:
result = make_plate(**design, outputs=outputs)
- for name, fmt, obj in result:
+ for output in result:
+ name, fmt, obj = output[:3]
if fmt == 'str':
continue
@@ -592,11 +624,16 @@ if __name__ == "__main__" or show_object:
if len(sys.argv) > 1:
outputs = sys.argv[1:]
- for name, fmt, obj in make_plate(**design, outputs=outputs):
+ for output in make_plate(**design, outputs=outputs):
+ name, fmt, obj = output[:3]
+ opt = None
+ if len(output) > 3:
+ opt = output[3]
+
filename = '{}.{}'.format(name, fmt)
print('generating "{}"...'.format(filename))
if fmt == 'str':
with open(filename, 'w') as f:
f.write(obj)
else:
- cq.exporters.export(obj, filename)
+ cq.exporters.export(obj, filename, opt=opt)