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authors-ol <s-ol@users.noreply.github.com>2020-05-28 12:42:14 +0000
committers-ol <s-ol@users.noreply.github.com>2020-05-28 12:42:14 +0000
commit95d8b69c68a17cf3fbcfb6d9f4752c9a90e9da69 (patch)
tree2083ed2af86124e9ddbf4811a5b7650d0a43f893 /README.md
parentdisassembly helper (diff)
downloadsubv-95d8b69c68a17cf3fbcfb6d9f4752c9a90e9da69.tar.gz
subv-95d8b69c68a17cf3fbcfb6d9f4752c9a90e9da69.zip
tests, cleanup, verify.py
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@@ -6,6 +6,14 @@ This is a wip clone of [SubX][mu] for the RISC-V RV31I base ISA.
$ ./test.py | ./elf.py > out.elf
$ ./qemu.sh out.elf
+Pipeline
+--------
+
+back to front:
+
+- `elf`: takes `hex.subx`-style input, outputs an ELF file
+- `survey`:
+
Debugging
---------