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authors-ol <s-ol@users.noreply.github.com>2020-05-28 16:28:07 +0000
committers-ol <s-ol@users.noreply.github.com>2020-05-28 16:28:07 +0000
commitd298144e6a5d6a0c52338100b73eadf4b33c5f09 (patch)
tree8b595d54677bfdcf58f0ec606f25c154712d6d71 /format.py
parentAdd ex.* (diff)
downloadsubv-d298144e6a5d6a0c52338100b73eadf4b33c5f09.tar.gz
subv-d298144e6a5d6a0c52338100b73eadf4b33c5f09.zip
cleanup
Diffstat (limited to 'format.py')
-rw-r--r--format.py113
1 files changed, 59 insertions, 54 deletions
diff --git a/format.py b/format.py
index b63a854..6a6a3b2 100644
--- a/format.py
+++ b/format.py
@@ -1,6 +1,6 @@
#!/usr/bin/env python3
-from subx import clean, classify, parse_segment, parse_instr, is_lref, untag, format_instr
-from riscv import u, i, bit_concat, bit_slice
+import subv
+import bits
instr_map = {
'opr': ('r', 0x33),
@@ -16,55 +16,55 @@ instr_map = {
def pack_u(instr):
(op, rd, imm) = instr
- op = u(untag(op), 7)
- rd = u(untag(rd, 'rd'), 5)
- if not is_lref(imm):
- imm = i(untag(imm, 'imm20'), 20)
+ op = bits.u(subv.untag(op), 7)
+ rd = bits.u(subv.untag(rd, 'rd'), 5)
+ if not subv.is_lref(imm):
+ imm = bits.i(subv.untag(imm, 'imm20'), 20)
return [op, rd, imm]
def pack_i(instr):
(op, sub, rd, rs, imm) = instr
- op = u(untag(op), 7)
- sub = u(untag(sub, 'subop'), 3)
- rd = u(untag(rd, 'rd'), 5)
- rs = u(untag(rs, 'rs'), 5)
- if not is_lref(imm):
- imm = i(untag(imm, 'imm12'), 12)
+ op = bits.u(subv.untag(op), 7)
+ sub = bits.u(subv.untag(sub, 'subop'), 3)
+ rd = bits.u(subv.untag(rd, 'rd'), 5)
+ rs = bits.u(subv.untag(rs, 'rs'), 5)
+ if not subv.is_lref(imm):
+ imm = bits.i(subv.untag(imm, 'imm12'), 12)
return [op, rd, sub, rs, imm]
def pack_s(instr):
(op, sub, rs1, rs2, imm) = instr
- op = u(untag(op), 7)
- sub = u(untag(sub, 'subop'), 3)
- rs1 = u(untag(rs1, 'rs'), 5)
- rs2 = u(untag(rs2, 'rs'), 5)
- if not is_lref(imm):
- imm = i(untag(imm, 'off12'), 12)
- imm_lo = bit_slice(imm, 4, 0)
- imm_hi = bit_slice(imm, 11, 5)
+ op = bits.u(subv.untag(op), 7)
+ sub = bits.u(subv.untag(sub, 'subop'), 3)
+ rs1 = bits.u(subv.untag(rs1, 'rs'), 5)
+ rs2 = bits.u(subv.untag(rs2, 'rs'), 5)
+ if not subv.is_lref(imm):
+ imm = bits.i(subv.untag(imm, 'off12'), 12)
+ imm_lo = bits.slice(imm, 4, 0)
+ imm_hi = bits.slice(imm, 11, 5)
else:
- label = untag(imm, 'off12')
+ label = subv.untag(imm, 'off12')
imm_lo = (label, 5, 'off12')
imm_hi = (label, 7, 'off12>>5')
return [op, imm_lo, sub, rs1, rs2, imm_hi]
def pack_j(instr):
(op, rd, imm) = instr
- op = u(untag(op), 7)
- rd = u(untag(rd, 'rd'), 5)
+ op = bits.u(subv.untag(op), 7)
+ rd = bits.u(subv.untag(rd, 'rd'), 5)
- if not is_lref(imm):
- imm = i(untag(imm, 'off21'), 21)
+ if not subv.is_lref(imm):
+ imm = bits.i(subv.untag(imm, 'off21'), 21)
if imm & 0b1 == 1:
raise ArgumentError("J-type offsets have to be halfword-aligned")
- imm_lo = bit_slice(imm, 10, 1)
- imm_11 = bit_slice(imm, 11, 11)
- imm_hi = bit_slice(imm, 19, 12)
- imm_20 = bit_slice(imm, 20, 20)
+ imm_lo = bits.slice(imm, 10, 1)
+ imm_11 = bits.slice(imm, 11, 11)
+ imm_hi = bits.slice(imm, 19, 12)
+ imm_20 = bits.slice(imm, 20, 20)
else:
- label = untag(imm, 'off21')
+ label = subv.untag(imm, 'off21')
imm_lo = (label, 10, 'off21>>1')
imm_11 = (label, 1, 'off21>>11')
imm_hi = (label, 8, 'off21>>12')
@@ -74,20 +74,20 @@ def pack_j(instr):
def pack_b(instr):
(op, sub, rs1, rs2, imm) = instr
- op = u(untag(op), 7)
- sub = u(untag(sub, 'subop'), 3)
- rs1 = u(untag(rs1, 'rs'), 5)
- rs2 = u(untag(rs2, 'rs'), 5)
- if not is_lref(imm):
- imm = i(untag(imm, 'off13'), 13)
+ op = bits.u(subv.untag(op), 7)
+ sub = bits.u(subv.untag(sub, 'subop'), 3)
+ rs1 = bits.u(subv.untag(rs1, 'rs'), 5)
+ rs2 = bits.u(subv.untag(rs2, 'rs'), 5)
+ if not subv.is_lref(imm):
+ imm = bits.i(subv.untag(imm, 'off13'), 13)
if imm & 0b1 == 1:
raise ArgumentError("B-type offsets have to be halfword-aligned")
- imm_lo = bit_slice(imm, 4, 1)
- imm_md = bit_slice(imm, 10, 5)
- imm_11 = bit_slice(imm, 11, 11)
- imm_12 = bit_slice(imm, 12, 12)
+ imm_lo = bits.slice(imm, 4, 1)
+ imm_md = bits.slice(imm, 10, 5)
+ imm_11 = bits.slice(imm, 11, 11)
+ imm_12 = bits.lice(imm, 12, 12)
else:
- label = untag(imm, 'off13')
+ label = subv.untag(imm, 'off13')
imm_lo = (label, 4, 'off13>>1')
imm_md = (label, 6, 'off13>>5')
imm_11 = (label, 1, 'off13>>11')
@@ -97,16 +97,10 @@ def pack_b(instr):
def format(iter):
for line in iter:
- line = clean(line)
- if line == '':
- continue
+ line = subv.parse(line)
- type = classify(line)
-
- if type == 'segment' or type == 'label':
- yield line
- else:
- instr = parse_instr(line)
+ if line['type'] == 'instr':
+ instr = line['instr']
op = instr[0]
if len(op) != 2:
raise ValueError("instruction without op label")
@@ -130,7 +124,9 @@ def format(iter):
else:
raise NotImplementedError()
- yield format_instr(out)
+ yield subv.format_instr(out)
+ else:
+ yield line['raw']
if __name__ == '__main__':
import sys
@@ -145,7 +141,7 @@ class TestPackers(unittest.TestCase):
final,
[(0x37, 7), (0x5, 5), (0x10010, 20)]
)
- self.assertEqual(bit_concat(*final)[1], 32)
+ self.assertEqual(bits.concat(*final)[1], 32)
label = pack_u([(0x37, 'lui'), (5, 'rd', 't0'), ('pos', 'imm20')])
self.assertEqual(
@@ -165,7 +161,7 @@ class TestPackers(unittest.TestCase):
final,
[(0x13, 7), (6, 5), (0, 3), (0, 5), (0x65, 12)]
)
- self.assertEqual(bit_concat(*final)[1], 32)
+ self.assertEqual(bits.concat(*final)[1], 32)
def test_pack_s(self):
final = pack_s([
@@ -179,7 +175,7 @@ class TestPackers(unittest.TestCase):
final,
[(0x23, 7), (0, 5), (2, 3), (5, 5), (6, 5), (0, 7)]
)
- self.assertEqual(bit_concat(*final)[1], 32)
+ self.assertEqual(bits.concat(*final)[1], 32)
label = pack_s([
(0x23, 'store'),
@@ -231,19 +227,27 @@ class TestE2E(unittest.TestCase):
out = dedent('''\
== code 0x80000000
main:
+ # load 0x10010000 (UART0) into t0
37/7 05/5 10010/20
+ # store 0x48 (H) in UART0+0
13/7 06/5 00/3 00/5 48/12
23/7 00/5 02/3 05/5 06/5 00/7
+ # store 0x65 (e) in UART0+0
13/7 06/5 00/3 00/5 65/12
23/7 00/5 02/3 05/5 06/5 00/7
+ # store 0x6c (l) in UART0+0
13/7 06/5 00/3 00/5 6c/12
23/7 00/5 02/3 05/5 06/5 00/7
+ # store 0x6c (l) in UART0+0
13/7 06/5 00/3 00/5 6c/12
23/7 00/5 02/3 05/5 06/5 00/7
+ # store 0x6f (o) in UART0+0
13/7 06/5 00/3 00/5 6f/12
23/7 00/5 02/3 05/5 06/5 00/7
+ # store 0x0a (\\n) in UART0+0
13/7 06/5 00/3 00/5 0a/12
23/7 00/5 02/3 05/5 06/5 00/7
+ # jump back up to the top
6f/7 00/5 main/8/off21>>12 main/1/off21>>11 main/10/off21>>1 main/1/off21>>20
''')
@@ -251,4 +255,5 @@ class TestE2E(unittest.TestCase):
for line in format(StringIO(inp)):
got += line + '\n'
+ self.maxDiff = None
self.assertEqual(got, out)