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authors-ol <s+removethis@s-ol.nu>2021-07-14 09:06:31 +0000
committers-ol <s+removethis@s-ol.nu>2021-07-14 09:06:31 +0000
commit04a224336adc788c03a243b86d7c2df4ee46a43f (patch)
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parentrename CSR instruction part /csr12 → /csr (diff)
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+<!DOCTYPE html>
+<html>
+ <head>
+ <title>SubV / RV32I reference</title>
+ <style>
+ html {
+ display: flex;
+ margin: 0;
+ padding: 0;
+ }
+ body {
+ flex: 0 0 auto;
+ display: flex;
+ flex-flow: column;
+ margin: 0;
+ padding: 1em;
+ width: auto;
+
+ font-family: "Source Code Pro", monospace;
+ background: #212121;
+ color: #eee;
+ }
+
+ h1 {
+ font-size: 1.5em;
+ font-weigh: normal;
+ margin: 0;
+ }
+
+ h2 {
+ font-size: 1em;
+ font-weight: bold;
+ margin: 0.5em 0 0;
+ }
+
+ table {
+ line-height: 1.75em;
+ }
+
+ table td, table th {
+ font-weight: normal;
+ padding: 0 1em;
+ }
+
+ table th {
+ text-align: left;
+ vertical-align: top;
+ }
+
+ .top td, .top th {
+ border-top: 1px solid currentColor;
+ }
+
+ .light {
+ background: #363636;
+ }
+
+ .src { color: #aae; }
+ .dst { color: #eaa; }
+ .jmp { color: #aea; }
+
+ .branch-op { color: #eea; }
+ .op-op, .op-mode { color: #eae; }
+ .sys-op { color: #aee; }
+
+ i {
+ font-style: normal;
+ }
+
+ a {
+ color: inherit;
+ text-decoration: underline;
+ }
+
+ a:hover {
+ color: #eea;
+ }
+ </style>
+ </head>
+ <body>
+ <h1>SubV / RV32I instruction set <b>reference</b></h1>
+ <h2>instructions</h2>
+ <table cellspacing="0">
+ <tr>
+ <th>
+ <i>37</i>/<b>lui</b>
+ </th>
+ <td>
+ <i>*</i>/<b class="reg dst">rd</b>
+ </td>
+ <td colspan="3"/>
+ <td>
+ <i>*</i>/<b class="imm src">imm20</b>
+ </td>
+ </tr>
+ <tr class="light">
+ <th>
+ <i>17</i>/<b>auipc</b>
+ </th>
+ <td>
+ <i>*</i>/<b class="reg dst">rd</b>
+ </td>
+ <td colspan="3"/>
+ <td>
+ <i>*</i>/<b class="imm src">off20</b>
+ </td>
+ </tr>
+ <tr>
+ <th>
+ <i>6f</i>/<b>jal</b>
+ </th>
+ <td>
+ <i>*</i>/<b class="reg dst">rd</b>
+ </td>
+ <td colspan="3"/>
+ <td>
+ <i>*</i>/<b class="imm jmp">off21</b>
+ </td>
+ </tr>
+ <tr class="light">
+ <th>
+ <i>67</i>/<b>jalr</b>
+ </th>
+ <td>
+ <i>*</i>/<b class="reg dst">rd</b>
+ </td>
+ <td>
+ <i>0</i>/<b>subop</b>
+ </td>
+ <td>
+ <i>*</i>/<b class="reg src">rs</b>
+ </td>
+ <td />
+ <td>
+ <i>*</i>/<b class="imm jmp">off12</b>
+ </td>
+ </tr>
+ <tr>
+ <th>
+ <i>63</i>/<b>branch</b>
+ </th>
+ <td />
+ <td>
+ <i>*</i>/<b class="branch-op">subop</b>
+ </td>
+ <td>
+ <i>*</i>/<b class="reg src">rs1</b>
+ </td>
+ <td>
+ <i>*</i>/<b class="reg src">rs2</b>
+ </td>
+ <td>
+ <i>*</i>/<b class="imm jmp">off13</b>
+ </td>
+ </tr>
+ <tr class="light">
+ <th>
+ <i>13</i>/<b>opi</b>
+ </th>
+ <td>
+ <i>*</i>/<b class="reg dst">rd</b>
+ </td>
+ <td>
+ <i>*</i>/<b class="op-op">subop</b>
+ </td>
+ <td>
+ <i>*</i>/<b class="reg src">rs</b>
+ </td>
+ <td />
+ <td>
+ <i>*</i>/<b class="imm src">imm12</b>
+ </td>
+ </tr>
+ <tr class="light">
+ <th>
+ <i>13</i>/<b>opi</b>
+ </th>
+ <td>
+ <i>*</i>/<b class="reg dst">rd</b>
+ </td>
+ <td>
+ <i>*</i>/<b class="op-op">subop</b>
+ <i>*</i>/<b class="op-mode">mode</b>
+ </td>
+ <td>
+ <i>*</i>/<b class="reg src">rs</b>
+ </td>
+ <td />
+ <td>
+ <i>*</i>/<b class="imm src">imm7</b>
+ </td>
+ </tr>
+ <tr>
+ <th>
+ <i>33</i>/<b>opr</b>
+ </th>
+ <td>
+ <i>*</i>/<b class="reg dst">rd</b>
+ </td>
+ <td>
+ <i>*</i>/<b class="op-op">subop</b>
+ <i>*</i>/<b class="op-mode">mode</b>
+ </td>
+ <td>
+ <i>*</i>/<b class="reg src">rs1</b>
+ </td>
+ <td>
+ <i>*</i>/<b class="reg src">rs2</b>
+ </td>
+ <td />
+ </tr>
+ <tr class="light">
+ <th>
+ <i>03</i>/<b>load</b>
+ </th>
+ <td>
+ <i>*</i>/<b class="reg dst">rd</b>
+ </td>
+ <td />
+ <td colspan="2">
+ <i>*</i>/<b class="width src">width</b>
+ <i>*</i>/<b class="reg src">rs</b>
+ <i>*</i>/<b class="imm src">off12</b>
+ </td>
+ <td />
+ </tr>
+ <tr>
+ <th>
+ <i>23</i>/<b>store</b>
+ </th>
+ <td colspan="2">
+ <i>*</i>/<b class="width dst">width</b>
+ <i>*</i>/<b class="reg dst">rd</b>
+ <i>*</i>/<b class="imm dst">off12</b>
+ </td>
+ <td>
+ <i>*</i>/<b class="reg src">rs</b>
+ </td>
+ <td colspan="2" />
+ </tr>
+ <tr class="light">
+ <th>
+ <i>73</i>/<b>system</b>
+ </th>
+ <td>
+ <i>*</i>/<b class="reg dst">rd</b>
+ </td>
+ <td>
+ <i>*</i>/<b class="sys-op">subop</b>
+ </td>
+ <td>
+ <i>*</i>/<b class="reg src">rs</b>
+ </td>
+ <td>
+ <i>*</i>/<b class="imm">csr</b>
+ </td>
+ <td />
+ </tr>
+ <tr class="light">
+ <th>
+ <i>73</i>/<b>system</b>
+ </th>
+ <td>
+ <i>*</i>/<b class="reg dst">rd</b>
+ </td>
+ <td>
+ <i>*</i>/<b class="sys-op">subop</b>
+ </td>
+ <td />
+ <td>
+ <i>*</i>/<b class="imm">csr</b>
+ </td>
+ <td>
+ <i>*</i>/<b class="imm src">imm5</b>
+ </td>
+ </tr>
+ <tr class="light">
+ <th>
+ <i>73</i>/<b>system</b>
+ </th>
+ <td />
+ <td>
+ <i>0</i>/<b class="sys-op">subop</b>/priv
+ </td>
+ <td />
+ <td colspan="2">
+ <i>0</i>/<b>funct12</b>/ecall
+ </td>
+ </tr>
+ <tr class="light">
+ <th>
+ <i>73</i>/<b>system</b>
+ </th>
+ <td />
+ <td>
+ <i>0</i>/<b class="sys-op">subop</b>/priv
+ </td>
+ <td />
+ <td colspan="2">
+ <i>1</i>/<b>funct12</b>/ebreak
+ </td>
+ </tr>
+ </table>
+ <h2>special parts</h2>
+ <table cellspacing="0">
+ <tr class="light">
+ <th colspan="2" rowspan="2">
+ <b>reg</b> (<b class="reg dst">rd</b>, <b class="reg src">rs*</b>)
+ </th>
+ <td>
+ 00/<b>zero</b> 01/<b>ra</b> 02/<b>sp</b> 03/<b>gp</b> 04/<b>tp</b>
+ </td>
+ <td>
+ 05/<b>t0</b>..07/<b>t2</b> 1c/<b>t3</b>..1f/<b>t6</b>
+ </td>
+ </tr>
+ <tr class="light">
+ <td>
+ 8/<b>s0</b> 9/<b>s1</b> 12/<b>s2</b>..1b/<b>s7</b>
+ </td>
+ <td>
+ 0a/<b>a0</b>..11/<b>a7</b>
+ </td>
+ </tr>
+ <tr>
+ <th colspan="2"><b>width</b></th>
+ <td>0/<b>b</b> 1/<b>h</b> 2/<b>w</b></td>
+ <td>4/<b class="src">bu</b> 5/<b class="src">hu</b></td>
+ </tr>
+ <tr class="light">
+ <th rowspan="4"><b>subop</b></th>
+ <th><b class="branch-op">branch</b></th>
+ <td>0/<b>==</b> 1/<b>!=</b> 4/<b>&lt;</b> 5/<b>>=</b></td>
+ <td>6/<b>&lt;u</b> 7/<b>>=u</b></td>
+ </tr>
+ <tr>
+ <th rowspan="2"><b class="op-op">opi</b>/<b class="op-op">opr</b></th>
+ <td colspan="2">
+ <i>00</i>/<b class="op-mode">mode</b>/norm:&emsp;
+ 0/<b>add</b> 1/<b>sll</b> 2/<b>slt</b> 3/<b>sltu</b>
+ 4/<b>xor</b> 5/<b>srl</b> 6/<b>or</b> 7/<b>and</b>
+ </td>
+ </tr>
+ <tr>
+ <td colspan="2">
+ <i>20</i>/<b class="op-mode">mode</b>/alt:&nbsp;&emsp;
+ 0/<b>sub</b> 5/<b>sra</b>
+ </td>
+ </tr>
+ <tr class="light">
+ <th><b class="sys-op">system</b></th>
+ <td>1/<b>csrrw</b> 2/<b>csrrs</b> 3/<b>csrrc</b></td>
+ <td>5/<b>csrrwi</b> 6/<b>csrrsi</b> 7/<b>csrrci</b></td>
+ </tr>
+ <tr>
+ <th><b>csr</b></th>
+ <td />
+ <td colspan="2">
+ see <a href="https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMFDQC-and-Priv-v1.11/riscv-privileged-20190608.pdf#section2.2">priviledged spec, sect 2.2</a>
+ </td>
+ </tr>
+ </table>
+ </body>
+</html>
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