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-rw-r--r--examples/hello_world.subv17
1 files changed, 9 insertions, 8 deletions
diff --git a/examples/hello_world.subv b/examples/hello_world.subv
index f74bc64..25a1cba 100644
--- a/examples/hello_world.subv
+++ b/examples/hello_world.subv
@@ -1,4 +1,4 @@
-== code 0x80400000
+== code 0x0
# load mhartid CSR into t0, trap all but first Hart
# 73/system 5/rd/t0 2/funct3/csrrs 0/rs/x0 f14/csr/mhartid
# 63/branch 1/subop/!= 5/rs/t0 0/rs/x0 0/off13
@@ -13,6 +13,7 @@ main:
6f/jal 1/rd/ra print/off21
exit:
+ 6f/jal 0/rd/x0 main/off21
# system reset (via SBI extension SRST)
# a7 = ext id, a6 = fid, a0 = 0, a1 = 0
37/lui 11/rd/a7 53525/imm20
@@ -24,20 +25,20 @@ exit:
73/system 0/subop/priv 0/funct12/ecall
print:
- # load 0x10000000 (UART0) into t0
- 37/lui 5/rd/t0 10000/imm20
+ # load 0x20000 (UART0) into t0
+ 37/lui 5/rd/t0 20/imm20
print:loop:
# load unsigned byte at a0
03/load 6/rd/t1 4/width/bu a/rs/a0 0/imm12
# break loop if zero
63/branch 0/subop/== 6/rs/t1 0/rs/x0 print:break/off13
print:spin:
- # spin if FIFO is full (thr_emtpy = UART+5 & 0x20)
- 03/load 7/rd/t2 4/width/bu 5/rs/t0 5/imm12
- 13/opi 7/rd/t2 7/subop/and 7/rs/t2 20/imm12
+ # spin if FIFO is full (UART+4 & 1 == 0)
+ 03/load 7/rd/t2 2/width/w 5/rs/t0 4/imm12
+ 13/opi 7/rd/t2 7/subop/and 7/rs/t2 1/imm12
63/branch 0/subop/== 7/rs/t2 0/rs/x0 print:spin/off13
# print char
- 23/store 2/width/w 5/rs/t0 0/off12 6/rs/t1
+ 23/store 2/width/w 5/rs/t0 8/off12 6/rs/t1
# increment a0
13/opi a/rd/a0 0/subop/add a/rs/a0 1/imm12
# jump back up
@@ -46,7 +47,7 @@ print:break:
# return
67/jalr 0/rd/x0 0/subop 1/rs/ra 0/off12
-== data 0x80500000
+== data 0x100
Message:
# "Hello World!\n\0"
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