subv - alternative RISC-V assembler

	Commit message (Expand)	Author	Files	Lines
2021-10-10	add optional strings stage	s-ol	1	-1/+22
2021-07-09	remove 0x prefix	s-ol	1	-7/+3
2021-07-09	wip more validation logic	s-ol	1	-1/+1
2021-07-06	fix and finish new pipeline	s-ol	1	-26/+5
2021-07-05	update format for new pipeline	s-ol	1	-2/+28
2021-07-05	update survey for new stage order	s-ol	1	-29/+21
2021-07-04	add validate layer	s-ol	1	-1/+1
2021-05-25	apply "black" formatting	s-ol	1	-67/+86
2021-05-25	update all stages to work	s-ol	1	-2/+3
2021-05-25	use new bits in format.py	s-ol	1	-2/+2
2021-05-24	turn bits into a class	s-ol	1	-2/+16
2021-05-23	support offsets on labels	s-ol	1	-2/+43
2021-05-23	revert to code detection by segment	s-ol	1	-8/+9
2021-05-22	log offending line when errors occur, across all stages	s-ol	1	-0/+42
2021-05-22	support non-byte aligned data lines	s-ol	1	-9/+15
2021-05-22	more error reporting in format.py	s-ol	1	-2/+19
2020-05-29	switch bit.py, subv.py to doctest	s-ol	1	-65/+170
2020-05-29	new label-slice syntax in format.py; switch to doctest	s-ol	1	-1/+37
2020-05-28	cleanup	s-ol	1	-21/+40
2020-05-28	survey, pack	s-ol	1	-3/+16
2020-05-28	tests, cleanup, verify.py	s-ol	1	-24/+78
2020-05-27	output emulatable .elf	s-ol	1	-0/+40